1. Field of the Invention
The present invention generally relates to a field effect transistor and a method of producing the field effect transistor, and more particularly, to a field effect transistor having a metallic gate, a metallic source, and a metallic drain.
2. Description of the Related Art
Recently an MOS LSI is being increasingly miniaturized while complying with the so-called scaling rule and is highly integrated. As a result of this, the degree of integration of the LSI is increasing four fold every three years, and in 2004, it was attempted to fabricate an LSI having a gate length of 90 nm. With a MOS LSI being highly miniaturized and thus highly integrated, the circuit can operate at a higher speed, whereas power consumption of each circuit decreases. Because of these advantages, miniaturization of the LSI at a higher level is being developed.
An MOS LSI is constituted by field effect transistors (FET), in each of which a pn junction is formed between source and drain regions, acting as electrodes for supplying a current, and a channel region due to implantation of a trivalent or pentavalent impurity into a silicon substrate.
With an MOS LSI being highly miniaturized, problems occur, such as a short channel effect, or increase of stray capacitance. To eliminate these problems, it is required to form more miniaturized impurity regions such as extension regions or pocket regions. However, with an MOS LSI being highly miniaturized, it becomes more and more difficult to form and control miniaturized impurity diffusion regions because of the difficulty in implantation position control and thermal diffusion control in the highly miniaturized MOS LSI. As a result, yields of FETs and LSIs degrade.
To solve this problem, a field effect transistor is proposed to have a metallic gate, a metallic source and a metallic drain instead of the impurity diffusion regions. In such a field effect transistor, as the source and drain are formed from metallic materials, it is easy to control positions of the source and drain, and the source and drain regions essentially do not change in the later fabrication steps. Hence, it is easy to make a design, and it may also help realize position control at the atomic level.
For example, Japanese Laid-Open Patent Application No. 2002-118175 and Japanese Laid-Open Patent Application No. 2000-22139 disclose techniques in this field.
In the field effect transistor having metallic source and drain regions, however, because the source and drain regions directly contact a channel region in a silicon substrate, a Shottky barrier can be formed as a result of metal-semiconductor contact, which prevents injection of carriers into the channel region. For example, in an n-channel FET, a Shottky barrier may be formed between the metallic source and the channel region, and this barrier prevents injection of electrons into the channel region. As a result, electrons cannot be injected into the channel region at a high concentration, and sufficiently high driving current cannot be obtained.